The present invention relates to the testing of integrated circuits, and in particular, to the preparation of a chip scale package prior to electrical characterization of the package.
Electrical components utilizing integrated circuit chips are used in a number of applications. Controlled Collapsed Chip Connection is an interconnect technology developed as an alternative to wire bonding. This technology is generally known as C4 technology, or flip chip packaging. Broadly stated, one or more integrated circuit chips are mounted above a single or multiple layer substrate and pads on the chip are electrically connected to corresponding pads on a substrate by a plurality of electrical connections, such as solder bumps. The integrated circuit chips may be assembled in an array such as a 10xc3x9710 array. A substrate is then electrically connected to another electronic device such as a circuit board with the total package being used in an electronic device such as a computer.
It is desirable to perform an electrical characterization of an integrated circuit by measuring inductance (L), capacitance (C), and resistance (R) at electrical contacts of the integrated circuit. This has presented a problem, however, when measuring these parameters for a xe2x80x9cchip scale package.xe2x80x9d Semiconductor dice, or chips, are typically individually packaged for use in plastic or ceramic packages. This is sometime referred to as the first level of packaging. The package is required to support, protect, and dissipate heat from the die and to provide a lead system for power and signal distribution to the die. The package is also useful for performing burn-in and functionality testing of the die.
One type of semiconductor package is referred to as a xe2x80x9cchip scale package.xe2x80x9d Chip scale packages are also referred to as xe2x80x9cchip size packages,xe2x80x9d and the dice are referred to as being xe2x80x9cminimally packaged.xe2x80x9d Chip scale packages can be fabricated in xe2x80x9cuncasedxe2x80x9d or xe2x80x9ccasedxe2x80x9d configurations. Uncased chip scale packages have a footprint that is about the same as an unpackaged die. Cased chip scale packages have a peripheral outline that is slightly larger than an unpackaged die. For example, a footprint for a typical cased chip scale package can be about 1.2 times the size of the die contained within the package.
Typically, a chip scale package includes a substrate bonded to the face of the die. The substrate includes the external contacts for making outside electrical connections to the chip scale package. The substrate for a chip scale package can comprise flexible material, such as a polymer tape, or a rigid material, such as silicon, ceramic, or glass. The external contacts for one type of chip scale package includes solder balls arranged in a dense array, such as a ball grid array xe2x80x9cBGA,xe2x80x9d or a fine ball grid array xe2x80x9cFBGA.xe2x80x9d These dense arrays permit a high input/output capability for the chip scale package. For example, a FBGA on a chip scale package can include several hundred solder balls.
In order to test the electrical characteristics of the integrated circuit, test probes are used to contact individual solder balls. Performing precise measurements of the electrical characteristics on a chip scale package is very difficult, however, due to the dimensions. It is hard to isolate a single solder ball or other electrical contact, while grounding the remainder of the solder balls. Hence, isolation and testing of a single, selected solder ball of an integrated circuit has proven to be a difficult task.
One of the reasons for the problems in performing electrical characterization of a chip scale package is the difficulty of simultaneously grounding all of the solder balls that are to be grounded on the package. Even with modern sophisticated manufacturing techniques, the solder balls of a ball grid array on a chip scale package will typically have heights that are slightly different from one another. It is possible to simultaneously ground all of the solder balls of a ball grid array with a flat conductive plate placed against the solder balls, but only if the conductive plate contacts each one of the balls. This can occur if the solder balls are the same height, but is problematic when the balls are of different heights, as the conductive plate will contact only the highest solder balls.
There is a need for a method of ensuring that all of the electrical contacts (e.g., solder balls) of a chip scale package make proper contact to a grounding surface of an electrical test fixture.
This and other needs are met by embodiments of the present invention which provide a method of performing electrical characterization of a chip scale package, comprising the steps of applying impressionable material on a contact surface of an isolation plate of a test fixture. The isolation plate is then placed on the tops of an array of electrical contacts of a chip scale package such that the impressionable material contacts at least some of the tops of the electrical contacts. After placement, the isolation plate is pressed against the array of electrical contacts such that at least some of the electrical contacts make an impression in the impressionable material. The impressions in the impressionable material are then examined.
By examining the impressions made in the impressionable material by the pressing of the electrical contacts, the coplanarity of the tops of the electrical contacts can be determined. Due to uneven heights, some of the electrical contacts (the taller ones) will leave deeper impressions in the impressionable material, while other contacts (the shorter ones), will leave less deep impressions or no impressions at all. These latter contacts will not be properly grounded when a grounding plate is later applied on top of the electrical contact array during an electrical characterization process. If it is determined, through the present invention, that the tops of the electrical contacts are not properly coplanar, the chip scale package can be discarded, or a corrective measure can be taken to planarize the tops of the electrical contacts. Once the coplanarity of the electrical contacts is assured, a flat grounding plate can be applied to the array to simultaneously ground all of the electrical contacts, except for a selected subset of the contacts that are isolated for testing.
The earlier stated needs are met by other embodiments of the invention, which provide a method of preparing a chip scale package having a plurality of electrical contacts for electrical characterization. The method comprises the steps of determining non-planarity of tops of the electrical contacts in an array of the chip scale package, and planarizing the tops of the electrical contacts as a function of the determination of non-planarity of the tops of the electrical contacts.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.